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? semiconductor components industries, llc, 2006 july, 2006 ? rev. 2 1 publication order number: ncp1337/d ncp1337 pwm current?mode controller for free running quasi?resonant operation the ncp1337 combines a true current mode modulator and a demagnetization detector which ensures full borderline/critical conduction mode in any load/line conditions together with minimum drain voltage switching (quasi?resonant operation). the transformer core reset detection is done internally, without using any external signal, due to the soxyless concept. the frequency is internally limited to 130 khz, preventing the controller to operate above the 150 khz cispr?22 emi starting limit. by monitoring the feedback pin activity, the controller enters ripple mode as soon as the power demand falls below a predetermined level. as each restart is softened by an internal soft?start, and as the frequency cannot go below 25 khz, no audible noise can be heard. the ncp1337 also features an efficient protective circuitry which, in presence of an overcurrent condition, disables the output pulses and enters a safe burst mode, trying to restart. once the default has gone, the device auto?recovers. also included is a bulk voltage monitoring function (known as brown?out protection), an adjustable overpower compensation, and a v cc ovp. finally, an internal 4.0 ms soft?start eliminates the traditional startup stress. features ? free?running borderline/critical mode quasi?resonant operation ? current?mode ? soft ripple mode with minimum switching frequency for standby ? auto?recovery short?circuit protection independent of auxiliary voltage ? overvoltage protection ? brown?out protection ? two externally triggerable fault comparators (one for a disable function, and the other for a permanent latch) ? internal 4.0 ms soft?start ? 500 ma peak current drive sink capability ? 130 khz max frequency ? internal leading edge blanking ? internal temperature shutdown ? direct optocoupler connection ? dynamic self?supply with levels of 12 v (on) and 10 v (off) ? spice models available for transient and ac analysis ? these are pb?free devices* typical applications ? ac?dc adapters for notebooks, etc. ? offline battery chargers ? consumer electronics (dvd players, set?top boxes, tvs, etc.) ? auxiliary power supplies (usb, appliances, tvs, etc.) pdip?7 p suffix case 626b pin connections device package shipping ? ordering information NCP1337PG pdip?7 (pb?free) 50 units/tube http://onsemi.com marking diagram a = assembly location wl = wafer lot y, yy = year ww = work week g = pb?free package = pb?free package (top view) fb bo cs gnd drv hv vcc ncp1337p awl yywwg 1 soic?7 d suffix case 751u ncp1337dr2g soic?7 (pb?free) 2500 tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 1 2 3 4 8 6 5 p1337 ayww 1 8
ncp1337 http://onsemi.com 2 pin function description pin no. symbol function description 1 bo brown?out and external triggering ? by connecting this pin to the input voltage through a resistor divider, the controller ensures operation at a safe mains level. ? if an external event brings this pin above 3.0 v, the controller?s output is disabled. ? if an external event brings this pin above 5.0 v, the controller is permanently latched?off. 2 fb sets the peak current setpoint ? by connecting an optocoupler or an auxiliary winding to this pin, the peak current setpoint is adjusted accordingly to the output power demand. ? when the requested peak current setpoint is below the internal standby level, the device enters soft ripple mode. 3 cs current sense input and overpower compensation adjustment ? this pin senses the primary current and routes it to the internal comparator via an l.e.b. ? inserting a resistor in series with the pin allows to control the overpower compensation level. 4 gnd ic ground 5 drv output driver ? to be connected to an external mosfet. 6 vcc ic supply ? connected to a tank capacitor (and possibly an auxiliary winding). ? when v cc reaches 18.6 v, an internal ovp stops the output pulses. 8 hv high?voltage pin ? connected to the high?voltage rail, this pin injects a constant current into the v cc bulk capacitor and ensures a clean lossless startup sequence. 1 8 2 3 4 6 5 ncp1337 rcomp bo + c bulk + v cc v cc + v out figure 1. typical application schematic
ncp1337 http://onsemi.com 3 figure 2. internal circuit architecture + gnd bo 5 v + ? + 3 v disable 10 a vdd + ? bok 7.5 s min period sstart ton clk d r1 r2 q q s soxyless demag detection dr v startup s q r v cc < 4 v perm. latch vdd tsd tsd soxyless 8 s timeout 35 s max toff 5.5 s blanking toff v cc soxyless v bo + 500 mv ovp + ? sskip skip setpoint + ? + ? 20 khz low?pass filter vdd fb 3 v 500 mv fault if zener activated vdd ton v bo 70 a x v bo ? 35 a cs 2 p 4 k 350 ns leb cs comp. 300 s soft?skip sskip 4 ms soft?start sstart perm. latch 67 s max ton fault management* fault (*if fault duration > 80 ms = > stop restart when 2nd time vcc = vccon) tsd inhib toff ton + ? + 12 v 10 v 5 v hv 9.5 ma or 600 a vc c + ? + ovp 18.6 v 100 mv 130 mv + ton
ncp1337 http://onsemi.com 4 maximum ratings rating symbol value unit voltage on pin 8 (hv) when pin 6 (v cc ) is decoupled to ground with 10 f v hv ?0.3 to 500 v maximum current in pin 8 (hv) ? 20 ma power supply voltage, pin 6 (v cc ) and pin 5 (drv) v ccmax ?0.3 to 20 v maximum current in pin 6 (v cc ) ? 30 ma maximum voltage on all pins except pin 8 (hv), pin 6 (v cc ) and pin 5 (drv) ? ?0.3 to 10 v maximum current into all pins except pin 8 (hv), pin 6 (v cc ) and pin 5 (drv) ? 10 ma maximum current into pin 6 (drv) during on time and t blank ? 1.0 a maximum current into pin 6 (drv) after t blank during off time ? 15 ma thermal resistance, junction?to?case r jc 57 c/w thermal resistance, junction?to?air, soic v ersion r ja 178 c/w thermal resistance, junction?to?air, dip v ersion r ja 100 c/w maximum junction t emperature tj max 150 c operating temperature range ? ?40 to +125 c storage temperature range ? ?60 to +150 c esd capability, hbm model per mil?std?883, method 3015 (all pins except hv) ? 2.0 kv esd capability, machine model ? 200 v maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limi t values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be af fected. 1. this device contains latchup protection and exceeds 100 ma per jedec standard jesd78.
ncp1337 http://onsemi.com 5 electrical characteristics (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, max t j = 150 c, v cc = 11 v, unless otherwise noted.) characteristic pin symbol min typ max unit supply section v cc increasing level at which the controller starts 6 vcc on 11 12 13 v v cc decreasing level at which the controller stops 6 vcc min 9.0 10 11 v protection mode is activated if v cc reaches this level whereas the hv current source is on 6 vcc off ? 9.0 ? v v cc decreasing level at which the latch?off phase ends 6 vcc latch 3.6 5.0 6.0 v margin between v cc level at which latch fault is released and vcc latch ? v margin 0.3 ? ? v v cc increasing level at which the controller enters protection mode 6 vcc ovp 17.6 18.6 19.6 v v cc level below which hv current source is reduced 6 vcc inhib ? 1.5 ? v internal ic consumption, no output load on pin 5, f sw = 60 khz 6 icc1 ? 1.2 ? ma internal ic consumption, 1.0 nf output load on pin 5, f sw = 60 khz 6 icc2 ? 2.0 ? ma internal ic consumption, latch?off phase, v cc = 8.0 v 6 icc3 ? 600 ? a internal ic consumption in skip 6 icc low ? 600 ? a internal startup current source minimum guaranteed startup voltage on hv pin 8 v hvmin ? ? 55 v high?v oltage current source when v cc > vcc inhib (v cc = 10.5 v, v hv = 60 v) 8 ic1 5.5 9.5 15 ma high?v oltage current source when v cc < vcc inhib (v cc = 0 v, v hv = 60 v) 8 ic2 0.3 0.6 1.1 ma leakage current flowing when the hv current source is off (v cc = 17 v, v hv = 500 v) 8 i hvleak ? ? 90 a drive output output voltage rise?time @ cl = 1.0 nf, 10?90% of output signal 5 t r ? 50 ? ns output voltage fall?time @ cl = 1.0 nf, 10?90% of output signal 5 t f ? 20 ? ns source resistance 5 r oh ? 20 ? sink resistance 5 r ol ? 8.0 ? temperature shutdown temperature shutdown ? tsd 130 ? ? c hysteresis on t emperature shutdown ? ? ? 30 ? c current comparator maximum internal current setpoint (@ i fb = i fb100% ) 3 v cslimit 475 500 525 mv minimum internal current setpoint (@ i fb = i fbripplein ) 3 v csripplein ? 100 ? mv internal current setpoint for i fb = i fbrippleout 3 v csrippleout ? 130 ? mv propagation delay from current detection to gate off state 3 t del ? 120 150 ns leading edge blanking duration 3 t leb ? 350 ? ns internal current offset injected on the cs pin during on time (over power compensation) @ 1.0 v on pin 1 and vpin3 = 0.5 v @ 2.0 v on pin 1 and vpin3 = 0.5 v 3 i opc ? ? 35 105 ? ? a maximum on time 5 maxt on 52 67 82 s
ncp1337 http://onsemi.com 6 electrical characteristics (continued) (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, max t j = 150 c, v cc = 11 v, unless otherwise noted.) characteristic pin symbol min typ max unit feedback section fb current under which fault is detected 2 i fbopen ? 40 ? a fb current for which internal setpoint is 100% 2 i fb100% ? 50 ? a fb current above which drv pulses are stopped 2 i fbripplein ? 220 ? a fb current under which drv pulses are reauthorized after having reached i fbripplein 2 i fbrippleout ? 205 ? a fb current above which fb pin voltage is not regulated anymore 2 i fbregmax ? 500 ? a fb pin voltage when i fbopen < i fb < i fbregmax 2 v fb 2.8 3.0 3.2 v duration before entering protection mode after fault detection ? t fault ? 80 ? ms internal soft?start duration (up to v cslimit ) ? t ss ? 4.0 ? ms internal soft?skip duration (up to v cslimit ) ? t sskip ? 300 ? s brown?out and latch section brown?out detection level 1 v bo 460 500 540 mv current flowing out of pin 1 when brown?out comparator has t oggled 1 i bo ? 10 ? a vpin1 threshold that disables the output 1 v disable 2.8 3.0 3.3 v vpin1 threshold that activates the permanent latch 1 v latch 4.75 5.0 5.25 v demagnetization detection block current threshold for demagnetization detection 5 i soxyth ? 210 ? a max voltage on drv pin during off time after t blank (when sinking 15 ma) 5 v drvlowmax ? ? 1.5 v min voltage on drv pin during off time after t blank (when sourcing 15 ma) 5 v drvlowmin ?0.6 ? ? v propagation delay from demag detection to gate on state (i gate slope of 500 a/s) 5 t dmg ? 180 220 ns blanking window after gate off state before detecting demagnetization 5 t blank ? 5.5 ? s timeout on demag signal 5 t out ? 8.0 ? s maximum off time 5 maxt off ? 35 42 s minimum switching period 5 minperiod 6.8 7.7 8.5 s
ncp1337 http://onsemi.com 7 application information introduction the ncp1337 implements a standard current mode architecture where the switch?off time is dictated by the peak current setpoint, whereas the core?reset detection triggers the turn?on event. this component represents the ideal candidate where low part?count is the key parameter, particularly in low?cost ac?dc adapters, consumer electronics, auxiliary supplies, etc. due to its high?performance, high?voltage technology, the ncp1337 incorporates all the necessary features needed to build a rugged and reliable switch?mode power supply (smps): ? quasi?resonant operation: valley?switching operation is ensured whatever the operating conditions are, due to the internal soxyless circuitry. as a result, there are virtually no primary switch turn?on losses, and no secondary diode recovery losses, and emi and video noise perturbations are reduced. the converter also stays a first?order system and accordingly eases the feedback loop design. ? dynamic self?supply (dss): due to its very high voltage integrated circuit (vhvic) technology, on semiconductor?s ncp1337 allows for a direct pin connection to the high?voltage dc rail. a dynamic current source charges up a capacitor and thus provides a fully independent v cc level. as a result, low power applications will not require any auxiliary winding to supply the controller. in applications where this winding is anyway required (see ?power dissipation? section in the application note), the dss will simplify the v cc capacitor selection. ? overcurrent protection (ocp): when the feedback current is below minimum value, a fault is detected. if this fault is present for more than 80 ms, ncp1337 enters an auto?recovery soft burst mode. all pulses are stopped and the v cc capacitor discharges down to 5.0 v. then, by monitoring the v cc level, the startup current source is activated on and off to create a burst mode. after the current source being activated twice, the controller tries to restart, with a 4.0 ms soft?start. if the fault has gone, the smps resumes operation. if the fault is still there, the burst sequence starts again. the soft?start, together with a minimum frequency clamp, allow to reduce the noise generated in the transformer in short?circuit conditions. ? overvoltage protection (ovp): by continuously monitoring the v cc voltage level, the ncp1337 stops switching whenever an overvoltage condition is detected. ? brown?out detection (bo): by monitoring the level on pin 1 during normal operation, the controller protects the smps against low mains condition. when pin 1 level falls below 500 mv, the controller stops pulsing until this level goes back and resumes operation. by adjusting the resistor divider connected between the high input voltage and this pin, start and stop levels are programmable. ? over power compensation (opc): an internal current source injects out of pin 3 (cs pin) a current proportional to the voltage applied on pin 1. as this voltage is an image of the input voltage, by inserting a resistor in series with pin 3, it is possible to create an offset on the current sense signal that will compensate the effect of the input voltage variation. ? external latch trip point: by externally forcing a level on pin 1 (e.g., with a signal coming from a temperature sensor) greater than 3.0 v (but below 5.0 v), it is possible to disable the output of the controller. if the voltage is forced over 5.0 v, the controller is permanently latched?off: to resume normal operation, the v cc voltage should go below 4.0 v, which implies to unplug the smps from the mains. ? standby ability: under low load conditions, ncp1337 enters a soft?skip mode: when the cs setpoint becomes lower than 20% of the maximum peak current, output pulses are stopped, then switching is starting again when fb loop forces a setpoint higher than 25%. as this occurs at low peak current, with soft?skip activated, and as the t off is clamped, noise?free operation is guaranteed, even with a cheap transformer.
ncp1337 http://onsemi.com 8 v cc cs setpoint cs fault timer 80 ms vcc on vcc min fault v csstby v cslimit ss when faul t is activated, the 80 ms timer starts. at startup, a 4.0 ms soft?start is activated. if the current setpoint is above the fault level, fault flag is raised. when the timer ends, if fault is not activated anymore, the controller works normally. timing diagrams figure 3. startup sequence
ncp1337 http://onsemi.com 9 v cc cs setpoint cs fault timer 80 ms vcc on vcc min fault v cslimit ss vcc latch restart on 2 nd cycle when the current setpoint rises above fault level, fault flag is activated. when fault flag is activated, timer is restarted. overload overload is removed here output pulses are stopped. 80 ms fault t imer normal startup figure 4. overload
ncp1337 http://onsemi.com 10 vcs rippleout vcs ripplein cs (envelope) min t on cs setpoint vcc min vcc on vcc soft?start on each re?start figure 5. soft ripple mode in standby
ncp1337 http://onsemi.com 11 soxyless the ?valley point detection? is based on the observation of the power mosfet drain voltage variations. when the transformer is fully demagnetized, the drain voltage evolution from the plateau level down to the v in asymptote is governed by the resonating energy transfer between the l p transformer inductor and the global capacitance present on the drain. these voltage oscillations create current oscillation in the parasitic capacitor across the switching mosfet (modelized by the crss capacitance between gate and drain): a negative current (flowing out of drv pin) takes place during the decreasing part of the drain oscillation, and a positive current (entering into the drv pin) during the increasing part. the drain valley corresponds to the inversion of the current (i.e., the zero crossing): by detecting this point, we always ensure a true valley turn?on. lprim crss drv isoxy vswitch t swing t figure 6. soxyless concept the current in the power mosfet gate is: igate = vringing/zc (with zc the capacitance impedance) so igate = vringing (2 fres crss) the magnitude of this gate current depends on the mosfet, the resonating frequency and the voltage swing present on the drain at the end of the plateau voltage. the dead time t swing is given by the equation: tswing 0.5 fres *lp*cdrain (eq. 1) (where l p is the primary transformer inductance and c drain the total capacitance present on the mosfet drain. this capacitance includes the snubber capacitor if any, the transformer windings stray capacitance plus the parasitic mosfet capacitances c oss and c rss ). internal feedback circuitry to simplify the implementation of a primary regulation, it is necessary to inject a current into the fb pin (instead of sourcing it out). but to have a precise primary regulation, the voltage present on fb pin must be regulated. figure 8 gives the fb pin internal implementation: the circuitry combines the functions of a current to voltage converter and a voltage regulator. fb + ? + 3 v vdd internal setpoint 20 khz low?pass filter figure 7. internal implementation of fb pin
ncp1337 http://onsemi.com 12 the input information is the current injected in fb pin by the feedback loop. the range of current is from 40 a for overload detection to 220 a corresponding to v csripplein . in transients, currents from 0 to more than 400 a may also appear: the circuitry is able to sustain them. to regulate the fb pin voltage, the operational amplifier needs to have a high gain and a wide bandwidth. but the feedback information used internally needs to be filtered, because we don?t want the controller to be sensitive to the switching noise. for this purpose, a 20 khz filter is added after the shunt regulator, and any reading of the feedback signal (for ripple mode, fault detection, or setpoint elaboration) is done after. soft burst mode (protection mode) the ncp1337 features a fault timer to detect an overload completely independently of the v cc voltage. as soon as the feedback loop asks for the maximum power, a fault is detected, and an internal timer is started. when the fault disappears the timer is reset, but if the timer reaches 80 ms, the protection mode is activated. once this protection is toggled, output pulses are stopped and dss is deactivated (hv current source turn?on threshold changes from vcc min to vcc latch ). v cc slowly decreases (the current consumption is icc3), and the hv current source is switched on when v cc reaches vcc latch . as a result v cc increases until vcc on , but the controller does not start as the output is still forced low. v cc decreases again down to vcc latch , and a new start?up cycle occurs. on the second attempt, the output is released, and ncp1337 effectively starts, with the soft?start activated. figure 4 illustrates this behavior. safety features the ncp1337 includes several safety features to help the power supply designer to build a rugged design: ? ovp (overvoltage on v cc ): activated when voltage on pin v cc is higher than 18.6 v ? brown?out (undervoltage lockout on bulk voltage): activated when voltage on pin bo is below 500 mv ? disable (comparator activated by an external signal): activated when the voltage on bo pin is higher than 3.0 v but below 5.0 v ? tsd (temperature shutdown): typically activated when the die temperature is above 150 c, released at 120 c all these events have the same consequence for the controller: the drv pulses are stopped. when the condition disappears, the controller restarts with the soft?start activated. ? permanent latch (comparator activated by an external signal): activated when the voltage on bo pin is above 5.0 v when this comparator is activated, the drv pulses are stopped, and the dss is deactivated (only the start?up current source is turned on each time v cc reaches vcc latch , maintaining v cc between 5.0 v and 12 v): the controller stays in this position until the v cc voltage is decreased below 4.0 v, i.e., when the power supply is unplugged from the mains (in normal operation, as soon as a voltage is present on the hv pin, v cc is always kept above 5.0 v). soft ripple mode the soft ripple mode is a skip mode with a large hysteresis on the skip comparator in order to ensure a noise?free and high?efficiency operation in low?load conditions (standby). when internal setpoint is reaching v csripplein = 100 mv (corresponding to 20% of the maximum setpoint), the output pulses are stopped. then fb loop asks for more power and internal setpoint is increasing: when it reaches v csrippleout = 130 mv (corresponding to 25% of the maximum setpoint), the output starts pulsing again. soft?start is activated in each activity following a stop period. see figure 5 for detailed timing diagram. hv current source ncp1337 features a dss, to allow operation without any auxiliary voltage. but to protect the die in case of short?circuit on v cc pin, the current delivered by the hv current source is lowered when v cc voltage is below 1.5 v. in the case the current consumed on the drv pin is higher than the dss capability (high qg mosfet or failure), the hv current source is switched on when v cc reaches vcc min , but the voltage on v cc pin keep on decreasing. if there is no uvlo threshold to stop the drv pulses, the gate voltage will become too low and the risk is high to destroy the mosfet. ncp1337 features an additional comparator, which threshold is 9.0 v: when v cc reaches this level whereas the hv current source is on, drv pulses are stopped and the protection mode is activated. brown?out the brown?out protection comparator has a fixed reference of 500 mv. when the comparator is activated (i.e., when the input voltage v in is above the starting level), a 10 a internal current source is activated and creates an offset across the bottom resistor of the external resistor divider. it gives the minimum hysteresis of the brown?out protection. by adding a series resistor between the divider and the bo pin, it is possible to adjust (increase) the hysteresis. the bo pin also features two additional comparators: the first one (that toggles at 3.0 v) stops the drv pulses, whereas the second one (that toggles at 5.0 v) permanently latches off the controller (the v cc should be forced below 4.0 v to release the latch). figure 8 gives the internal implementation of the bo pin.
ncp1337 http://onsemi.com 13 + ? + 5 v permanent latch + ? + 3 v enable vdd 10 a current source activated when v bok is high + ? + 500 mv bok bo rhyst v in 3.3 meg 11 k figure 8. internal implementation of bo pin package dimensions soic?7 d suffix case 751u?01 issue c seating plane 1 4 5 8 r j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b are datums and t is a datum surface. 4. dimension a and b do not include mold protrusion. 5. maximum mold protrusion 0.15 (0.006) per side. s d h c dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?a? ?b? g m b m 0.25 (0.010) ?t? b m 0.25 (0.010) t s a s m 7 pl
ncp1337 http://onsemi.com 14 package dimensions pdip?7 p suffix case 626b?01 issue a notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension l to center of lead when formed parallel. 4. package contour optional (round or square corners). 5. dimensions a and b are datums. 14 5 8 f note 2 ?t? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max millimeters a 9.40 10.16 b 6.10 6.60 c 3.94 4.45 d 0.38 0.51 f 1.02 1.78 g 2.54 bsc h 0.76 1.27 j 0.20 0.30 k 2.92 3.43 l 7.62 bsc m ??? 10 n 0.76 1.01 a b on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 ncp1337/d soft?skip is a trademark of semiconductor components industries, llc (scillc). the product described herein (ncp1337), may be covered by the following u.s. patents: 6,362,067, 5,073,850, 6,385,060, 6,587,35 7, 6,469,484, 6,940,320, 5,862,045. there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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